Weekend Course for RTL Design and Verification

Digital Design Basics

• • The importance of Number System in Data Representation.
  • Different Optimization techniques using Boolean algebra.
  • Gate level optimization
  • Karnaugh Maps.
  • A new Truth Table method that avoids laborious process of Karnaugh Map optimization.
  • Developing the basic building blocks for Combinational Logic Circuits and implementing different Logical Expressions using the same.
  • Evolution of the Sequential Elements-Latches and Flip Flops.
  • Design of Synchronous Sequential Machines-Synchronous Detectors, Counters and Registers.

Advanced Digital Design

• • Flip Flop timing parameters
  • Critical path and operating frequency of the system.
  • Design of Hybrid Counters.
  • Design of complex Sequence detectors.
  • Design of Control FSMs based on the specifications.
  • Design of Frequency synthesizers.

CMOS Basics

• • Acquire the knowledge about various CMOS fabrication process.
  • NMOS and PMOS operation.
  • CMOS characteristics.
  • CMOS inverter rise, fall and propagation delays.
  • CMOS second order effects.
  • Analyse and implement various functions using CMOS circuits.
  • CMOS Flip flop and its timing parameters

Verilog HDL

• • Digital design flow and Design methodologies.
  • Understanding Behavioural description, RTL Design and Gate level design.
  • Understand the origin of the Verilog HDL language
  • Understand the language basics
  • Use of Verilog HDL building blocks (design units) including modules, ports, processes, and assignments
  • Model code styles for behavioural code style and Structural code style
  • Understand the design methodologies of Verilog HDL and the differences between simulation models and synthesis models.
  • Difference between Synthesizable and Non-Synthesizable constructs.
  • Discriminate between combinatorial and Sequential circuit design.
  • Writing Synthesizable Verilog code.
  • Write a Verilog test bench to test Verilog Modules

RTL Design using VERILOG HDL along with Project

• • Understanding the intent of RTL design.
  • RTL design guidelines.
  • Race conditions.
  • Analysis of Synchronous and Asynchronous behaviour.
  • Understanding CDC.
  • To design combinational, sequential circuits using Verilog HDL.
  • To understand behavioural and RTL modelling of digital circuits
  • To verify that a design meets its timing constraints, both manually and through the use of computer aided design tools
  • To simulate, synthesize, and program their designs.

RTL Design using System Verilog HDL

• • Understanding RTL Design.
  • Understanding basics of CDC and DFT.
  • System Verilog data types.
  • System Verilog procedural blocks and statements.
  • Usage of System Verilog Interface in RTL design.
  • Parameterized Interfaces and Modports.
  • Usage of Generate and Genvar in RTL design for multi-master and multi-slave configuration.
  • Design of synchronous machines using System Verilog.
  • Design of memory block using System Verilog.

RTL Verification using VERILOG HDL

• • Understanding Verification types.
  • Verification flow.
  • Test bench architecture.
  • Developing Test bench components.
  • Simulation and Synthesis mis-matches.
  • Test bench models.
  • Understanding X-propagation.
  • Timing Verification-Gate level simulation.

System Verilog Basics

• • Verification Challenges
  • New data types available in System Verilog.
  • Interfaces and Clocking Blocks.
  • Various new verification building blocks available in System Verilog.
  • Developing a basic Verification environment.
  • Introduction to OOPs concepts
  • Introduction to Advanced concepts like Randomization, Constraints, and Assertions and Coverage.

Verification using System Verilog

• • System Verilog Basics
  • New features
  • New Data type additions
  • Arrays – Fixed, Packed, Dynamic, Queues, Associated
  • Structures & Unions
  • New Operators
  • New additions to Subroutines
  • New additions to Procedural statements& Control flow
  • Concurrency
  • Interfaces
  • Program block
  • Virtual Interfaces
  • Inter thread Synchronization & Communication
  • System Verilog OOPs
  • Classes: Encapsulating properties & methods
  • Object memory creation
  • Working with Object handles
  • Object copying: Shallow and Deep copy
  • Object protection
  • Object variables Vs Class variables: Static keyword
  • Object Inheritance
  • Limitations of Inheritance
  • Polymorphism and Methods overriding
  • Randomization and Constraints
  • Object Randomization
  • Randomization Seed
  • Randomization variables
  • Constraint Block
  • Weighted Randomization
  • Controlling Randomization
  • Solve order
  • Inline Constraints – with constraints
  • System Verilog Assertions
  • Immediate assertions
  • Procedural assertions
  • Temporal operators
  • Boolean operators
  • Sequences
  • Properties
  • Test Bench Design Using System Verilog
  • Introduction to Layered test bench architecture
  • Driver
  • Monitor
  • Transactor
  • Generator
  • Configurations – Device, Transaction
  • Scoreboard
  • Reference models
  • Bus function models
  • System Verilog Functional Coverage
  • PROJECT: Protocol Verification

UVM Structural Overview

• • Key Takeaways
  • Key Concepts in UVM: Agent, Environment and Tests
  • Implement UVM Testbenches for Re-Use across Projects
  • Code, Compile and Run UVM Tests
  • Inner Workings of UVM Simulation including Phasing
  • Implement and Manage User Report Messages
  • Modelling Stimulus (UVM Transactions)
  • Transaction Property Implementation Guidelines
  • Transaction Constraint Guidelines
  • Transaction Method Automation Macros
  • User Transaction Method Customization
  • Use Factory Override to Control Transaction Constraints
  • Creating Stimulus Sequences (UVM Sequence)
  • Implementing User Sequences
  • Using UVM Macros to create and manage Stimulus
  • Explicitly Execute Sequences in Test
  • Implicitly Execute Sequences Through Configuration in Environment
  • Sequence Execution Protocol
  • Phase Objection
  • UVM Factory and Callbacks
  • Establish and Query Component Parent-Child Relationships
  • Set Up Component Virtual SystemVerilog Interfaces with uvm_config_db
  • Constructing Components and Transactions with UVM Factory
  • Implement Tests to Configure Components
  • Implement Tests to Override Components with Modified Behavior
  • TLM Communications
  • Scoreboard & Coverage
  • Implement scoreboard with UVM In-Order Class Comparator
  • Implement scoreboard UVM Algorithmic Comparator
  • Implement Out-Of-Order Scoreboard
  • Implement Configuration/Stimulus/Correctness Coverage
  • UVM Callback
  • Create User Callback Hooks in Component Methods
  • Implement Component Functional Coverage with User Defined Callbacks
  • Review Default Callbacks in uvm_sequence Base Class
  • Advance Sequence/Sequencer
  • Implement Top Level Sequence and Sequencer to Manage Sequence Execution within Different Agents
  • Disable Selected Sequencer in Agents through the Sequencer’s “default” Configuration Field
  • Phasing and Objections
  • Managing Objections within Component Phases
  • Implement Component Phase Domain Synchronization
  • Implement User Defined Domain and Phases
  • PROJECT: Protocol Verification